Similarly, Intel processor graphics is treated as a unique agent on the interconnect ring. Every on-die CPU core is regarded as a unique agent. This SoC ring interconnect is a bi-directional ring that has a 32-byte wide data bus, with separate lines for request, snoop, and acknowledge. The on-die bus used on Skylake between CPU cores, caches, and Intel processor graphics is a ring based topology with dedicated local interfaces for each connected agent. The architecture implements multiple unique clock domains, which have been partitioned as a perCPU core clock domain, a processor graphics clock domain, and a ring interconnect clock domain.

You can see that Intel is using a single shared silicon die for their SoC that features multiple CPU cores, Intel processor graphics, and potentially other fixed functions all on a single shared silicon die. The figure above offers a very high level look at the Intel 6th generation Core i7-6700K processor.

His whitepaper covers how Intel used the new gen9 architecture for the Intel HD Graphics 530 in the recently released Intel Core i7 processor 6700K for desktop form factors and other upcoming processors that will be released in the near future. All that changed overnight when a whitepaper titled ‘ The Compute Architecture of Intel Processor Graphics Gen9‘ was published by Stephen Junkins just hours ahead of the Intel Developer Forum (IDF) that takes place in San Francisco this week. We knew that Intel HD 530 Graphics was the based on Intel processor graphics gen9 architecture, but other than being told that the graphics product naming conventions changed with gen9, from 4 digits to 3 we were left in the dark as to what Intel actually did on Skylake to improve graphics performance.

The Intel 6th Generation Core i7-6700K and Core i5-6600K ‘Skylake’ processors feature Intel HD Graphics 530, but when the processors were released little was said about the Intel HD 530 Graphics.

Intel hd 530